乐曲硬件演奏电路设计
《EDA技术与VHDL》实验报告
一、实验设计要求
学习利用实验6-3的数控分频器设计硬件乐曲演奏电路,即设计电子琴,硬件测试可用实验电路模式3。
二、设计原理
主系统由三个模块组成，有TONETABA.VHD,NOTETABS.VHD和SPCAKERA.VHD,
三、实验程序
library ieee;--songer主程序
use ieee.std_logic_1164.all;
entity songer is
port(clk12mhz:in std_logic;
clk8hz:in std_logic;
code1:out std_logic_vector(3 downto 0);
high1:out std_logic;
spkout:out std_logic);
end;
architecture one of songer is
component notetabs
port(clk:in std_logic;
toneindex:out std_logic_vector(3 downto 0));
end component;
component tonetaba
port(index:in std_logic_vector(3 downto 0);
code:out std_logic_vector(3 downto 0);
high:out std_logic;
tone:out std_logic_vector(10 downto 0));
end component;
component speakera
port(clk:in std_logic;
tone:in std_logic_vector(10 downto 0);
spks:out std_logic);
end component;
signal tone:std_logic_vector(10 downto 0);
signal toneindex:std_logic_vector(3 downto 0);
begin
u1:notetabs port map(clk=>clk8hz,toneindex=>toneindex);
u2:tonetaba port map(index=>toneindex,tone=>tone,code=>code1,high=>high1);
u3:speakera port map(clk=>clk12mhz,tone=>tone,spks=>spkout);
end;
library ieee;--speaker程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity speakera is
port( clk:in std_logic;
tone:in std_logic_vector(10 downto 0);
spks:out std_logic);
end;
architecture one of speakera is
signal preclk,fullspks:std_logic;
begin
divideclk:process(clk)
variable count4:std_logic_vector(3 downto 0);
begin
preclk<='0';
if count4=15 then preclk<='1';count4:="0000";
elsif clk'event and clk='1' then count4:=count4+1;
end if;74