FPGA图像处理系统关键问题研究
时间:2018-07-08 11:34 来源:毕业论文 作者:毕业论文 点击:次
| 摘要数字图像处理在近年来发展迅速，在科研、民用领域上的运用也越来越广泛。而基于FPGA的数字图像处理系统也逐渐成为了主流。在该系统中，需要存储器来暂存来自视频编码模块发出的数字视频图像信号，同步动态随机储存器SDRAM是其中运用最为广泛的存储器之一。本设计是一采用状态机思路进行开发的，用Verilog硬件描述语言编写的，基于FPGA的SDRAM控制器。设计过程采用自顶向下的设计思路，底层模块分别实现状态机控制、SDRAM指令解析、读写数据暂存与输入输出的功能，再通过顶层模块将其连接，实现对SDRAM进行精确的时序控制，根据用户请求在特定地址进行数据读写操作的功能。最后，设计成功通过仿真与逻辑分析并移植到一现有的数字图像处理系统上。本设计能够通过简单改编移植到不同的数字图像处理系统上，有较强的普适性。 关键词 数字图像处理系统 SDRAM控制器 FPGA 毕业设计说明书外文摘要 Title Research on the Key Problem of Image Processing System based on FPGA Abstract In recent decades, digital image processing has been rapidly developed and been more popular in both scientific researching and civilian fields. And digital image processing system based on FPGA is gradually becoming the main stream. In that system, a storage module is needed to keep the digital video data generated by the video encoded module and synchronous dynamic random access memory is one of the most popular choices. The project is a SDRAM controller based on FPGA which is designed using the method of Finite State Machine and programmed by Verilog hardware description language. The whole designing process follows the Top_Down design thoughts. The top module connects all the bottom modules that realize the following functions separately, state machine control, SDRAM commands decoding and controlling the data transfer. Through this, the design can accurately control the SDRAM time sequence, allowing users to read (write) data from (to) the specific address of the SDRAM. At the end of the design process, the project was simulated and tested by SignalTap Logic Analysis Tool and successfully transplanted to an existing digital image processing system. The design can be easily transplanted to different digital image processing systems for only few modifications is needed. Therefore, the design has relatively high universality. Keywords Digital Image Processing System SDRAM controller FPGA 目 次 1 绪论 1 1.1 国内外研究背景 1 1.2 课题研究意义 2 1.3 主要研究内容 3 2 SDRAM时序控制 4 2.1 SDRAM时序分析 4 2.2 SDRAM时序控制方法 9 3 SDRAM控制器的设计 11 3.1 SDRAM控制器核心模块设计 11 3.1.1 有限状态机模块 12 3.1.2 命令解析模块 13 3.1.3 数据通路模块 14 3.2 读写FIFO设计 14 3.3 其余辅助模块设计 16 3.3.1 数据产生模块 16 3.3.2 分频倍频器 16 3.4 模块连接 17 4 SDRAM控制器的仿真与调试 18 4.1 SDRAM控制器功能仿真 18 4.1.1 初始化仿真结果 18 4.1.2 自刷新仿真 20 4.1.3 写数据操作时序仿真 20 4.2 SDRAM控制器下载与调试 20 4.2.1 SDRAM控制器调试结果 20 (责任编辑：qin) |