The output signal V1(z) of the first stage is given by: 

V z1( ) = STF z1( )⋅U z( )+ NTF z1( )⋅E1( )z ,       (6) 

where STF1(z), NTF1(z) and E1(z) are the signal transfer function, the noise transfer function and the error of the first-stage loop respectively。  The output signal V2(z) of the second stage is given by 

V2( )z = STF2( )z ⋅E1( )z + NTF2( )z ⋅E2( )z ,      (7) 

where STF2(z), NTF2(z) and E2(z) are respectively the signal transfer function, the noise transfer function and the error of the second-stage loop。  If the digital filter stages H1 and H2 at the output of the two modulator loops are set to satisfy the condition H1·NTF1(z)–H2·STF2(z)=0, in the overall output V(z) of the system the first-stage error E1(z) is cancelled whatever 

Fig。 4。 Structure of the two-stage MASH Δ-Σ modulator。 

the output V(z) is。  Usually the choice for H1 and H2 is H1=k·STF2 and H2=k·NTF1, where k is a constant chosen to give unity signal gain and STF2 is often a delay [13]。  For k=1, the overall output signal is then given by 

V z( ) = H1 ⋅V z1( ) − H2 ⋅V2( )z

= STF1 ⋅STF2 ⋅U z( )− NTF1 ⋅ NTF2 ⋅E2( )z 。    (8) 

In practical implementation both stages of the MASH ∆-Σ modulator may contain a first-order or a second-order loop。 

Compared to the single-stage ∆-Σ modulator (shown in Fig。 3), the MASH structure (shown in Fig。4) has the ability to extract the first-stage error e1(n) without any subtraction and then enter it into the second stage with low distortion。  Besides, the remaining error in the output signal V(z) is the shaped quantization error e2(n) of the second stage, operating with an input error e1(n) which is itself noise-like。  Hence, the second-stage quantization error e2(n) is very similar to a true white noise [13]。 

Supposing the internal loop is first-order, setting 

STF1 = STF2 =1,NTF1 = NTF2 = (1− z−1) ,       (9) 

H1 = STF2 =1,H2 = NTF1 = (1− z−1),        (10) 

we get the overall output as 

V z( ) =U z( )−(1− z−1 2) ⋅E2( )z 。          (11) 

Thus, the MASH ∆-Σ modulator has the noise-shaping performance of a second-order loop but the stability issue is that of a first-order one。  Similarly, for a second-order internal loop, the MASH ∆-Σ modulator has the noise-shaping performance of a fourth-order loop while the stability issue acts as a second-order one。 

A MASH ∆-Σ modulator with two first-order internal loops is applied for the proposed Hybrid ∆-Σ DPWM in this paper。  The schematic diagram of the proposed DPWM based on two-stage MASH ∆-Σ is shown in Fig。5。  The two cascaded first-order internal loops result in a global second-order-loop noise-shaping while preserving the first-order-loop robust stability property。  Here, STF1 = STF2 = 1, NTF1 = NTF2 = (1–z–1), H1 = STF2 = 1, H2 = NTF1 = (1–z–1) and V(z) = U(z) – (1–z–1)2·E2(z)。  The 11-bit DPWM duty value from control algorithm is sent to the first-stage loop, then 4-MSB for output and 7-LSB for error-feedback e1。  After the second-stage loop, the 2-MSB is delivered for output and 5-LSB for error-feedback e2。 

Fig。 5。 Schematic diagram of the proposed DPWM based on two-stage MASH Δ-Σ modulator。 

Finally the 6-bit combination PWM signal (4-MSB and 2-MSB) is sent to the Core DPWM (DLL phase-shift and counter-comparator blocks)。 

B。 4-bit segmented DCM phase-shift block