The maximum frequency breadth for on SDRAM is 166MHz and the frequency of image sensor is 25MHz。 The Image Mosaic Module is working in 25MHz。 The SDRAM controller has two pair Read and Write interface which has 16bit data breadth。 If the 30bit image should be obtained, the four ports are all in use。 Thus, the frequency breadth ( FB ) should present:

In the stream format of 4:4:4, the subsample of each

FB 25MHz 2 25MHz 2 100MHz

(7)

component signal is equivalent。 The information of each pixel  in  the  image  is  complete。  There  are  four pixels:

{ Y0 ,U0 ,V0 }, { Y1,U1,V1 }, { Y2 ,U2 ,V2 }, { Y3 ,U3 ,V3 }。

The stream format is

Y0 ,U0 ,V0 ,Y1,U1,V1,Y2 ,U2 ,V2 ,Y3 ,U3 ,V3 。

In the stream format of 4:2:2, the U and V component signal is half of Y component signal。 The total amount of the stream is compress by 33%。 There still are four pixels:

{ Y0 ,U0 ,V0 }, { Y1,U1,V1 }, { Y2 ,U2 ,V2 }, { Y3 ,U3 ,V3 }。

The stream format is Y0 ,U0 ,Y1,V1,Y2 ,U2 ,Y3 ,V3 。 The pixels that reconstitute are: { Y0 ,U0 ,V1 }, { Y1,U0 ,V1 },

{ Y2 ,U2 ,V3 }, { Y3 ,U2 ,V3 }。

In the analysis above, the format of 4:4:4 does not compress the data and is not suitable for embedded system。 The format of 4:2:2 will bring complicated time sequence for swap the component signal while in the process of compressing and bring the possibility of image distortion。 Since the bound of SDRAM is 16bit, we optimize the format of signal stream。 In the odd line, we collect Y and U component signal and collect Y and V component signal in the even line。 There are eight pixels in two lines:文献综述

Line  1:  { Y0 ,U0 ,V0  },  { Y1,U1,V1 },  { Y2 ,U2 ,V2 },

{ Y3 ,U3 ,V3 }

Line  2:  { Y4 ,U4 ,V4 },  { Y5 ,U5 ,V5 },  { Y6 ,U6 ,V6  },

{ Y7 ,U7 ,V7 }。

Sine the value of (7) is less than 166MHz, the solution is suit for the condition and the SDRAM controller is shown in Fig。 7。

E。Fast Fourier Transform Module

For realization of the FFT as a hardware circuit, the butterfly operation plays an important role [23]。 Effective description  of  the  butterfly  operation  gives  small  size

Figure 8。   The Structure of FFT Module。

Figure 9。 The Consequence of the test for FFT module。

circuits of FFT [24]。 In this paper, an improved FFT  unit

is presented。 We rearrange the pipeline of butterfly operation and separate the butterfly operation to two levels。 The compute results can be saved by their parity rather than ordinal method [25]。

The  N ( N 2M (M Z ) ) points FFT, for  instance,

V。

ETHERNET INTERFACE

A。Design of Ethernet Interface

Using Ethernet interface of panoramic mosaic camera, the data packet is sent to the remote client by related network   protocols   which   include   RTP/RTCP,  UDP,

adopt  2M 1  pipeline。   The

yi   present   the   calculate

HTTP  and  TCP/IP。  The  traditional  solution  is    using

consequence of level j 。 The process is

⎧ N

TCP/IP protocol stack which is running in the NIOS II processor based on the RTOS of embedded system [26], [27]。  Thus,  the  network  structure  is  pided  into  four

layers: Physical Layer, Data Link Layer, Net Layer and Transfer Layer。 To achieve the requirement of    real-time

⎩⎪ y j 1 (2i  N )  y j1 (2i 1 N ), i [ 2 , N )