摘要基于 FPGA 全数字锁相环电机调速系统的设计，涉及到 FPGA 技术、锁相环技术以 及自动控制技术。基于 FPGA 的开发，自上而下进行系统设计，是当下电子设计的主 流。 全数字锁相环进行电机调速，并非传统的以速度差作为调节量，而是以相位差作 为控制量进行电机调速，其调速精度高，电机调节跟踪速度快，抗干扰能力较强。全 数字锁相环采用同步时钟控制。本设计详细的介绍了锁相环的基本理论及应用，并分 析在系统设计中的问题和难点。其次，为实现电机锁相环系统的调速功能，形成了软 件的设计方案 ，包括数字鉴相器，环路滤波器、数控振荡器、PWM 生成模块。再次， 对全数字锁相环调速系统建立数学模型。最后在实验平台上验证所设计的全数字锁相 环电机调速系统的调速效果。84537
毕业论文关键词: FPGA 数字锁相环 自动控制 电机调速
Abstract The Design of motor speed control system are based on FPGA and all digital phase locked loop。FPGA technology, phase locked loop technology and automatic control technology are involved in this design。The system design based on FPGA technology is top-down。 System development using FPGA is the mainstream of the current electronic design。Using all digital phase locked loop for motor speed regulation is different from the traditional motor speed control。The adjustment of the traditional motor speed regulation is the speed difference。However, the control of this design is the phase difference。Using the phase difference of the speed to adjust the speed with high precision, fast tracking speed and strong anti-interference ability。All digital phase locked loop adopts synchronous clock control。This design details the basic theory and application of phase locked loop, and analyzes the problems and difficulties in the design of the system。Secondly, in order to realize the function of the motor speed control system, the software design scheme is formed, including digital phase detector, loop filter, digital control oscillator and PWM generation module。Thirdly, the mathematical model of the whole digital phase locked loop motor speed regulation system is established。Finally verifying the design of all digital phase locked loop speed control effect in the experimental platform。
Keywords: FPGA digital phase locked loop automatic control motor speed regulation
目录
第一章 绪论 1
1。1 FPGA 技术 1
1。2 锁相环的发展史 1
1。3 研究的目的和意义 3
1。5 论文的主要内容及章节安排 4
第二章 锁相环的基本理论 6
2。1 锁相环的基本结构 6
2。2 锁相环的基本性质 7
2。3 鉴相器 8
2。3。1 异或门鉴相器 8
2。3。2 JK 触发鉴相器 8
2。3。3 PFD 鉴频鉴相器 10
2。4 环路滤波器 13
2。5 数控振荡器 15
2。6 N 分频 16
2。6。1 输出为输入 N 倍频的方法 FPGA全数字锁相环电机调速系统设计:http://www.youerw.com/zidonghua/lunwen_100391.html