摘要尽管当下数字化广播电台的建设高速发展，但是与之配套的监测、控制系统却未实现同步，其效率较低，功能并不理想。本课题针对音频广播监测这一领域现状提供了一种系统设计方案，有较大的实用价值。本课题的工作可归结为信号格式转换，利用FPGA芯片对输入的音频数据解码，再转换成I2S格式信号传输给专用音频芯片，音频芯片将数字音频转换成模拟音频后输出，用户即可通过耳机收听到声音。 30063
本文首先介绍了广播电视行业普遍应用的AES/EBU音频接口标准和信号转换系统所使用的I2S总线标准，包括它们的采样频率、位宽和内含信息等，基于这些特点建立格式转换方案。
其次介绍了系统的总体设计，自顶向下地划分各个模块的功能，主要分为电平转换模块、信号解码模块和音频格式转换模块。另外还说明了确保系统功能实现的外围电路设计，包括电源、时钟部分。系统的主控部分由Alter公司的FPGA芯片EP1C3T144C8实现，包括音频信号的解码和格式转换，还有对数模转换模块的控制。实现数模转换的音频芯片选用了四片飞利浦公司的芯片UDA1341TS，分别对应完成四路I2S数字音频转换为模拟音频的功能。
之后详细阐述了信号的采样、解码、识别、提取和转换模块的设计，包括设计方法、部分程序和综合得到的RTL电路图。最后则给出了实物图和调试结果，并对运行结果进行分析，提出了总结和展望。
关键词：AES/EBU标准音频流，FPGA，I2S总线标准，L3控制，解码
毕业论文设计说明书外文摘要
Title Digital Audio Stream Processing and Output Design Based on FPGA
Abstract
Digital broadcast studio centers develop quite rapidly, but the monitoring and controlling systems for them are less modified at their efficiency and function. This paper works on the problems of these systems, then proposes a practical system based on transformation of the information format. Our work here includes decoding of input AES/EBU audio stream signals and transferring them into I2S, converting digital signals into analog audios, and trying the output audios by headphones.
The paper introduces the data structure and frequency of the two main audio formats referred here. One is the popular format in broadcast and radio areas, the AES/EBU standard audio stream signals; and the other one is necessary for the signal transformation part.
Then describes the designing of the whole system in a top-down way ,by introducing the functions of every part and the supporting circuits. The microcontroller in this system is the FPGA chip EP1C3T144C8 of Alter Company, and the digital-analog converting are achieved by four of the professional audio processing chips UDA1341TS of Philips Company, corresponding to the four channel of input broadcast signals.
Next part expatiates the sampling, decoding, recognizing and converting part for the signals, and provides the designing modalities, the core parts of Verilog HDL code paragraph, and the RTL viewer’s results. Last shows photos of hardware and the running results, then concludes the system by analyzing them and suggesting for future work.
Key words: AES/EBU standard audio stream, FPGA, I2S, L3, decode
目 次
1 绪论 1
1.1 课题背景2
1.2 本文研究内容与结构安排3
2 数字音频数据传输标准4
2.1 AES/EBU数字音频接口标准 4
2.2 I2S总线标准8
3 系统总体设计10
3.1 信号格式转换10
3.2 系统外围电路设计15 数字音频流的处理和音频输出的FPGA程序设计:http://www.youerw.com/tongxin/lunwen_25585.html