摘要本次毕业设计题目是“FPGA编程下载全定制电路设计”。用户使用可编程逻辑器件时，对器件的配置信息通过位流下载，传输到器件内部，写入对应的编程点。位流下载电路可以分为半定制电路和全定制电路两部分。半定制电路输出编程点的地址信息和对应的二进制配置信息给全定制电路，全定制电路对地址信息进行译码，使能相应编程点的字线 WL，并将二进制配置信息通过位线 BL 写入编程点，实现对器件的编程控制。此处的全定制电路称为DLWL/BL电路。而我的毕业设计论文研究的正是这DLWL/BL电路。61562

本论文在DLWL/BL电路的一些基本知识的基础上，采取了两种实现方式进行了电路设计，分别是电路图实现方式和Verilog代码实现方式，并对两种方式优缺点进行了对比，比较出了两种实现方式的优劣。最后对其中存在的电路问题提出了优化措施：采用门控时钟降低电路功耗。

毕业论文关键词  FPGA  编程下载  DLWL/BL   Verilog  门控时钟

毕业设计说明书（论文）外文摘要

Title      FPGA programming download full-custom    circuit design                                               

Abstract The graduation project entitled “FPGA programming download full-custom circuit design”.When using programmable logic devices, the device configuration information is downloaded to the device's internal through the bit stream, then written to the corresponding point in the programming. Download circuit of the bit stream can be pided into two parts of the semi-custom circuits and full-custom circuits. Semi-custom circuit output address information and corresponding binary configuration information of programming point to the full-custom circuit, then full-custom circuit decode the address information to enable WL of the corresponding programming point , and the binary configuration information is written to the programmed points through BL, to achieve the control for the programming of the device. The full-custom circuit is called DLWL / BL circuit. My graduation project is the DLWL / BL circuit. 

This paper based on some basic knowledge of the DLWL / BL circuit takes two methods to achieve the circuit design, namely circuit implementation and Verilog code implementation. Then I compare the advantages and disadvantages of two methods. Finally, there is a circuit problem which presents optimization measures: use gating clock to reduces power dissipation.

Keywords  FPGA  programming download  DLWL / BL  Verilog  gating clock

1  研究基础 1

1.1  FPGA架构  1

1.2  FPGA编程下载电路  1

1.3 FPGA编程下载全定制电路  … 2

1.3.1  整体架构  …2

1.3.2  DLWL电路介绍  …3

1.3.3  DLBL电路介绍  …5

2  DLWL/BL两种实现方式… 6

2.1  电路图实现  …6

2.1.1  DLWL电路设计  …6

2.1.2  DLWL电路仿真  …11

2.1.3  DLBL电路设计  …12

2.1.4  DLBL电路仿真  …16

2.2  Verilog代码实现  20

2.2.1  Verilog代码设计  …20

2.2.2  modelsim仿真22

3  DLWL/BL两种实现方式的对比 24

3.1  电路图实现方式优缺点  24

3.2  Verilog代码实现方式优缺点25

3.3  两种实现方式对比分析   25

4  其他优化措施… 27

4.1  采用门控时钟降低功耗   27 FPGA编程下载全定制电路设计:http://www.youerw.com/tongxin/lunwen_67373.html