FPGA的DDS激励PLL相位可控信号源设计

摘要本文首先介绍了几种主要的频率合成方式，然后详述了用DDS激励PLL的方法产生频谱纯净的相位可控线性调频源的实现过程。DDS可以实现信号源频率、幅度、相位改变的数字化，同时兼具相噪优良、频率间隔小、切换响应即时的优点。锁相环的闭环负反馈控制可以降低输出信号杂散。因此用DDS激励PLL的方式可以设计出一款高频率分辨率、高输出频率、低相噪、低杂散的相位可控信号源。65232

该信号源的DDS部分采用Cyclone系列FPGA芯片EP1C3T100C8控制DDS芯片AD9958产生两路相位不同的扫频信号，用于激励PLL。PLL部分采用单片机MSP430F2013控制鉴相芯片ADF4106，经过有源低通滤波器和VCO芯片HMC632LP5，产生工作频率为14.9GHz-15.1GHz的线性调频波。该线性调频源为三角形调频连续波，调制带宽200MHz，调制周期1ms，步进频率4KHz，步进时间10ns。经过测试，该信号源基本达到了性能指标要求。

毕业论文关键词：相位可控线性调频源直接数字频率合成锁相环

毕业设计说明书（论文）外文摘要

Title Design of Phase-Controlled Signal Source

Abstract

Firstly, several main methods of frequency synthesis are introduced in this paper. Then the realization of LFM(linear frequency modulated) source with

pure spectrum by using the method called“DDS drives PLL” is discussed in detail. DDS has such merits like fine frequency resolution、frequency agility and phase control. PLL has such merits like narrow-band tracing filter and wide scope of frequency multiplication. This hybrid technology combines the merits of DDS and PLL. Therefore, a phase-controlled signal source with fine frequency resolution、high frequency output and low phase noise can be realized.

The DDS section adopts Cyclone series FPGA chip-- EP1C3T100C8 controlling DDS chip AD9958 to generate two channels of frequency-sweep signal, which is used to drive PLL. The PLL section adopts MCU chip MSP430F2013 to control

phase discriminator ADF4106. Added with active low-pass loop filter and VCO chip HMC529LP5, it can produce LFM wave ranging from 14.9GHz to 15.1GHz. The waveform is continuous triangular frequency modulated wave with modulation bandwidth 200MHz, modulation period 1ms, step frequency 4KHz, and step time 10ns. The performance of designed signal source basically reaches requirements after test.

Keywords: Phase-Controlled LFM DDS PLL

1 绪论 1

1.1 研究的背景及意义 1

1.2 频率合成技术的几种主要实现方法 2

1.3 频率合成技术的发展近况 4

1.4 本课题采用的相位可控信号源设计实现方法 6

1.5 论文的组织安排 6

2 相位可控信号源的基本理论 8

2.1 线性调频信号的基本理论 8

2.2 DDS的基本理论 8

2.3 PLL的基本理论 9

2.4 频率杂散与相位噪声 10

3 相位可控信号源的设计方案 12

3.1 总体方案 12

3.2 芯片选型 13

4 相位可控信号源的电路设计 FPGA的DDS激励PLL相位可控信号源设计:http://www.youerw.com/tongxin/lunwen_72764.html