数字音频流的FPGA的AES流编解码监测系统设计

摘要现在数字化的范围越来越广泛，广播电台中数字音频信号也得到了极大地应用，电台通过卫星发射AES/EBU流节目信号，但是目前存在一些错播和漏播的情况，人工监测成本大，效率低。本文设计了一个AES流编解码监测系统，在发射信号的用户数据位插入特定的识别信息，在解码端进行比对可以实现自动监测播出状况。82424

本文首先介绍了AES编解码的意义，然后介绍了AES信号的数据结构，各个数据位代表的含义，并依此确定了编解码插入用户信息位的方案。本文详细描述了在FPGA平台上对AES信号进行编码和解码的过程，使用Altera公司 Cyclone系列 EP1C3T144C8信号进行了实际编解码实验。

最后给出了系统运行实际运行调试及结果展示，并提出了一些可以改进部分和后续工作的方向。

毕业论文关键词 AES信号编码解码 FPGA UDA1341ts

毕业设计说明书外文摘要

Title Design of FPGA encoding and decoding program for Digital audio stream

Abstract Now the digital range is more and more extensive, and the digital audio signal in the radio station has been greatly applied。The AES/EBU stream program signal is transmitted by the radio station, but now there are some errors in broadcasting, the cost of manual monitoring is high and the efficiency is low。In this paper, we design a AES streaming codec monitoring system, in which a specific identification information is inserted in the user data bits of the transmitted signal。Confirming the information at the decoding side can automatically monitor the status of the broadcast。This paper firstly introduces the meaning of AES encoding and decoding, and then introduces the data structure of AES signal, the meaning of each data bit, and then determines the scheme of encoding and decoding to insert the user's information bits。This paper describes in detail the process of encoding and decoding the AES signal on the FPGA platform, using the Cyclone series EP1C3T144C8 of the Alter company to carry out the actual coding and decoding experiment。Finally, the debugging of the system running and the results are presented, and some directions for the improvement of the system and the future work are put forward。

Keywords AES signal，coding，decoding，FPGA,UDA1341ts

1 引言 1

1。1 研究背景和意义 1

1。2 本文工作目标及整体构思 2

2 AES/EBU传输标准的信号结构 3

2。1 AES/EBU标准介绍 3

2。2 AES/EBU信号结构 3

2。3 AES/EBU信号编码方式 4

3 FPGA平台编码解码过程 6

3。1 FPGA介绍 6

3。2 解码 7

3。2。1 采样模块 7

3。2。2 定位前导码模块 9

3。2。3 解码模块 11

3。3 编码 15

3。4 先入先出缓存 18

3。5 本章小结 18

4 立体声数模转换器芯片控制 19

4。1数模转换器芯片介绍 19

4。2 L3端口控制字数字音频流的FPGA的AES流编解码监测系统设计:http://www.youerw.com/tongxin/lunwen_96717.html