摘要目前高分辨率雷达带宽不断提高，这就要求雷达存储系统拥有更大的存储容量和更高的存储速度。选择合适的存储器件是解决这个问题的关键。eMMC (Embedded Multi Media Card) 为MMC协会所订立的内嵌式存储器标准规格。eMMC在内部中集成了一个控制器，这是一个巨大的优势，它提供标准接口并管理内存，使得开发人员专注于开发存储产品的其它部分，这样就缩短产品的生产周期。目前对于eMMC设备的开发与应用成为存储系统的一个热点。82423

针对在数据存储系统在雷达领域所遇到的问题和需求，本文采用了一种基于FPGA对eMMC储存阵列的大容量高速数据读写控制的方法。采用四个三星eMMC5。0芯片作为存储阵列，内存大小为128G。选用FPGA作为主控芯片，根据eMMC5。0的协议通过Verilog编程来实现FPGA对eMMC芯片的读写控制。最终可实现200Mbits/S的写入速度，400Mbits/S的读出速度。

毕业论文关键字：FPGA    eMMC5。0   高速数据读写    Verilog

毕业设计说明书外文摘要

Title   Realization of Controlling eMMC 5。0 Device Based  on FPGA                                                 

Abstract With the continuous increasing of modern high resolution radar ‘s bandwidth, radar system have higher requirements for bulk data transfer and storage rates。 Choose the appropriate storage device is the key to solve this problem 。EMMC (Mutlimedia Card embedded) is a standard specification for embedded memory。 One obvious advantage of this is that a controller is integrated in the package。 It provide standard interface and manage flash memory。 This allows the user to focus on other parts of the system, to shorten the development time of the system。 At present, the development and application of eMMC equipment has become a hot spot of the storage system

  In view of the problems encountered and the requirement met in the data storage system in the field of radar, In this paper, a hardware solution for high speed and large capacity storage and a general FPGA control logic for eMMC memory device are proposed。 It realizes the control of eMMC and the operation of high speed reading and writing。 In the storage part, four Samsung's eMMC 5。0 chips are used as a storage array and the capacity is 128GB，and using FPGA as the main control chip。 According to the agreement of eMMC5。0, and with the programming in verilog , realizing the control of the read and write of the eMMC by FPGA。 EMMC array composed of multi eMMC chip meet 200M/S write speed and 400M/S read speed。

Key word：High speed data storage，FPGA，eMMC5。0，Verilog

目   录

1 绪论 3

1。1课题的研究背景和意义 3

1。2高速数据存储的国内外发展概况 4

1。3 eMMC存储储器的发展趋势 5

2 基于FPGA的eMMC控制器设计的总体方案 6

2。1引言 6

2。2总体方案选择 6

2。2。1系统功能需求 6

2。2。2总体方案确定 7

2。3 小节 8

3 ISE软件及IP核 9

3。1引言 9

3。2 ISE 软件 9

3。3 IP核 eMMC存储器的基于FPGA的数据读写控制:http://www.youerw.com/tongxin/lunwen_96715.html