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The clutch signal line 11 is acknowledged by cam interrupt signal line 13 10 5 25 30 35 40 50 55 6 generated by CAM A (operator paced) or CAM B (machine paced) via OR gate 71. Data sent to EZR 28 is latched in by CPU 70 “Lockout 1” pulse line 17 which is also synchronized at the proper time via CAM pulse line 11 and lockout signal line 15 from console 12. CPU 70 also initializes I/O Data Bus Controller 41 and Print Controller/Synchronizer 40. Further, CPU 70 evaluates keyboard data input and provides POSTNET bar code for printing. Timing pulses generated within CPU are produced by a 20 MHZ crystal connected directly thereto. Residing in PROM 73 is the program code, which is pided into three sections: Modes of Operation, Program Initialization and Table Lookup. Modes of Operation are selected by Mode Select 32. Program Initialization occurs upon power-up or reset. The Lookup Table cross references POSTNET code for digits 0 to 9 conversion. RAM 72 stores key code information identifying user-programmable keys pres ent on Keyboard 20. Also, RAM 72 is provided with a battery backup circuit to insure integrity of the memory upon power failure. Key code is programmed in via interaction of Keyboard 20, CPU 70, and the software program stored in PROM 73. The Print Controller/Synchronizer 40 controls and veri?es proper printing of A-field, 5 or 9 digit POST NET printing and B-?eld, expanded 5 t0 9 digit POST NET printing. Synchronization of POSTNET printing is accomplished by a photocell detector, within Mail Piece Detector 55. When the leading edge of the mail piece passes by the photocell, Mail Piece Detector 55 output line 57 goes low clearing Counter 59 and inter rupting CPU 70 via OR gate 53 output INT2. The trail ing edge of the mail piece pulls Mail Piece Detector 55 output line 57 high, identifying the beginning of the print cycle. The start count circuit 58 synchronizes the Mail Piece Detector 55 rising edge with the rising edge of encoder 56. Counter 59 is a binary counter. Required outputs are pulsed at predetermined times depending upon input signals 5/9 and A/B. With signals A/B and 5/9 set high the counter 59 counts to 32 and stops; if signal 5/9 is low it counts to 52. If printing is required in the B-?eld signal A/B is set low, the counter 59 generates a signal at count 37 and stops at count 72. The output from Counter 59 connected to Data Re quest 54 pulses every eight counts to send an interrupt to CPU 70 through OR gate 53. This requests eight more bits of data be sent to Shift Register 52. Data in Shift Register 52 is shifted by the Counter 59 Count Clock pulse. Also, the qbl output enables the acknowl edge signal to tell the I/O Data Bus Controller 41 that data has been accepted in Shift Register 52. Code Printer 10 on FIG. 4B is described as follows: Data from the Shift Register 52 arrives at Buffer 51 where the digital signals are converted to high current drive pulses . to activate the Print Head 50 for printing. The Print 60 65 Head is an impact pin printer consisting of 9 pins. If a “O” is shifted out of the Shift Register 52, the bottom 5 pins print a low bar, if a “1”, all 9 pins print a high bar. The mail piece, after it has been bar-coded, travels past a photo detector interface to the Bar Code Print Detec tor 61. The Print Detector 61 measures the print con trast ratio between the background and the bar print to insure that it is readable. The background is read when Counter 59 output “RB” is pulsed allowing a voltage to pass through the Read Background Analog Switch 60 and place the voltage charge on capacitor 63. Next the Counter 59 output “RC” is pulsed when bar print is in 7 front of the Detector 51 and allows this voltage to pass through Read Bar Code Analog Switch 62. The two voltages are compared with A/D Comparator 64.
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