摘要无线传感网（Wireless Sensor Network, WSN）是由传感器节点构成的网络，通过网络、集成传感器以及微机电系统三大技术，形成一种全新的信息获取与处理技术。频率合成器是无线收发机中射频前端的重要部分，为系统提供本地振荡信号。在基于锁相环的频率合成器中，分频器是一个十分重要的模块，它是频率合成器提供多个高精度频率信号且实现高频率低功耗工作的关键。

本文采用TSMC 0.18 μm CMOS工艺设计并实现了一个32/33双模分频器，它由高速二分频器、相位切换电路和异步分频器构成，双模分频器采用了改进的相位切换结构，降低了功耗。后仿真的结果表明，在1.8 V电源电压下，双模分频器的工作频率范围为4.2~5.6GHz，工作电流为2.429mA。版图设计中的芯片面积为166.54×97.12 μm2。64790

本文设计的高速二分频器已应用于WSN节点的频率合成器中。设计的双模分频器经过进一步的优化也可用于WSN射频收发机芯片或是其它无线通信RF收发机芯片中。

毕业论文关键词  无线传感网  锁相环  频率合成器  相位切换  双模分频器

毕业设计说明书（论文）外文摘要

Title  Design of the 5GHz Low-Power Divider for WSN Nodes 

Abstract

Wireless sensor network is a network consisting of sensor nodes, by using networks， integrated sensors, and electromechanical systems, a new processing technology has been formed. Frequency synthesizer (FS) is used to generate local oscillation (LO) signals in WSN transceiver system. In PLL-based FS，frequency pider is one of the most important building blocks, for it can provide high-accuracy multi-channel LO signals. 

A 32/33 dual-modulus pider is presented in this thesis for the WSN applications, which has three blocks, a high-speed frequency halving circuit, a phase switching circuit and a asynchronous pider. In the dual-modulus pider, an improved phase switching technique is used to reduce the power consumption. Implemented in TSMC 0.18 μm CMOS process, post simulation shows that the pider can operate over a wide range of 4.2~5.6GHz, consumes 2.429mA from a single 1.8 V supply voltage, and occupies a chip area of approximately 166.54×97.12 μm2.

The high-speed frequency halving circuit has been used in the WSN frequency synthesizer chip. The designed dual-modulus pider can be used in WSN RF transceiver chips and other wireless communication RF transceiver chips.

Keywords  WSN  PLL  Frequency Synthesizer  Phase Switching  Dual-Modulus Divider

目   次

1  绪论 1

1．1  课题背景及意义 1

1．2  研究现状 2

1．3  设计内容及指标 4

1．4  电路设计流程 4

1．5  论文组织结构 4

2  分频器的结构分析 6

2．1  频率合成器的结构和原理 6

2．2  数字分频电路与D触发器 7

2．3  高速D触发器的结构 9

2．4  双模分频器 13

3  应用于WSN节点的低功耗分频器设计