基于FPGA的视频图像降噪程序设计
关键词 FPGA VHDL 图像降噪处理 时域递归滤波 自适应递归降噪
毕业设计说明书（论文）外文摘要
Title Noise Reduction Program of Video Image Based On FPGA
Abstract
According to the video image information is often affected by various noise
in the process of production, transmission and recording, this paper
introduces one design of noise reduction processor in video image based
on FPGA.
This paper mainly introduces the algorithm of noise reduction in time
domain recursive filtering in the video image field, carries out the
recursive filter is the weighted average of the low pass filter. According
to the curve between filter coefficient and improved SNR, this paper
designs out an self-adaptive noise reduction processor based on the FPGA
platform, including three parts named judgment, operation, and SRAM
control. It also shows out the corresponding program written by VHDL and
achieves the desire result. Adaptive noise reduction processor selects
Altera Cyclone series FPGA as the core chip, with specific models for
EP1C20F400I7.
The whole design is simulated and synthesized on the Altera Quartus II 7.0
software.
Keywords FPGA VHDL Image Noise Reduction Time domain recursive
filter self-adaptive noise reduction filter
目 录
1 引言 1
1．1 研究背景 .. 1
1．2 视频降噪的研究意义 1
1．3 视频降噪算法的国内外研究现状 .. 2
2 视频图像概述 4
2．1 视频信号数字化 4
2．2 数字视频图像 .. 5
2．3 数字视频格式 ITU-RBT.656标准 .. 6
3 FPGA 概述 9
3．1 FPGA结构 . 9
3．2 FPGA开发流程 10
3．3 FPGA的选型 .. 12
3．4 FPGA的开发调试工具 .. 13
4 时域递归滤波算法 ... 14
4．1 递归滤波原理 . 14
4．2 时域递归滤波系数的选择 ... 16
5 自适应降噪处理器设计 ... 18
5．1 延时模块 . 19
5．2 图像降噪处理模块 . 21
5.2.1 判断模块 21
5.2.2 运算模块 23
5.2.3 对比度增强模块 .. 25
5．3 SRAM控制模块 25
5.3.1 SRAM 使能与读写控制模块 .. 26
5.3.2 数据流向控制模块 30
6 仿真及调试 . 30
结 论 33
致 谢 34
参 考 文 献 ... 35
1 引言
本章主要介绍视频图像降噪技术的研究背景、研究意义和国内外发展现状。