摘要：本次课题主要基于国产ELF系列CPLD开发板进行印制电路板设计和软件测试。本设计硬件方面进行开发板的核心板PCB设计，首先进行原理图的绘制，元件库制作，添加元件封装，BOM表导出，PCB的布局，连线，电气规则约束等。利用MAX II EPM570 CPLD芯片，主要实现24小时制的数字时钟功能，同时具有整点报时功能。且电路具有保护系统，保证了整个系统的有效执行，确保电路的安全稳定工作环境。本设计的优点在于既有PCB硬件的设计同时有程序测试相结合；本次设计的开发板提供了完整、随时可以使用的硬件平台，板上集成了大量的 I/O设备和CPLD所需的支持电路，能够构建无数的设计而不需要其他器件，降低了成本，便于软硬件调试。80692

毕业论文关键词： CPLD；PCB；数字时钟，ELF-650开发板

Design of CPLD development board based on domestic ELF series

Abstract： This project mainly based on domestic ELF series CPLD development board for printed circuit board test and software design The design of the hardware development board core board PCB design, the first schematic drawing, component library production, add component packaging, BOM table export, PCB layout, wiring, electrical rules, etc。。 Software mainly uses MAX II CPLD chip, the main achievement of 24 hours of digital clock function, with the whole point timekeeping function EPM570。 And the circuit has a protection system to ensure the effective implementation of the whole system to ensure the safety and stability of the working environment。 The advantage of this design is to design both hardware and software of the PCB test combination; provides a complete, ready to use in the design of hardware platform development, support circuit board integrated I/O equipment and a large number of CPLD required, to build numerous design without the need for other devices to reduce the cost for hardware and software debugging。

Key words: CPLD; PCB; Digital clocks; The ELF-650 development board

目录

1 引言 1

1。1 课题背景 1

1。2 课题目的和意义 2

1。3 课题的主要内容 2

2 总体方案设计 3

2。1 硬件平台选择 3

2。2 硬件描述语言 3

2。3 硬件描设计过程 3

2。4 系统工作过程 4

3 软硬件开发环境 5

3。1 硬件开发环境 5

3。1。1 Altium Designer 09 5

3。2 软件开发环境 7

3。2。1 Quartus II 13。0sp1 (64-bit) 7

3。2。2 TD软件 10

4 elf-650开发板原理图设计 12

4。1 ELF-650开发板原理图总览 12

4。2 EF1A650LG144 CPLD芯片介绍 12

4。3 XTAL晶振介绍 14

4。4 1117稳压器介绍 15

4。5 JTAG接口介绍 16

4。6 USB接口介绍 17

4。7 原理图电路连接 18

4。7。1 EF1A650LG144芯片电路连接 18

4。7。2 XTAL晶振电路连接