摘要如今,随着信息技术飞速的进步,集成电路技术也取得了跨越式的发展。在 计算机、航空航天、民用和军用电子中都广泛的应用到大规模集成电路的自动布 图技术。但是,将这种技术视为核心机密的世界著名的厂家都把此技术保护了起 来。在国内掌握集成电路核心技术的公司更是少之又少,因此市场前景非常广阔。72739
本篇主要讲述了超大规模集成电路布图规划的流程,以及布图规划的表示方 法。模拟退火算法(Simalated Annealing Algorithm,SA)被用来来解决超大规模 集成电路中布局的问题。讲解了超大规模集成电路的流程设计和其中最为关键的 物理设计流程。还有布图规划中的成本函数的构成,目的是使面积和线长达到最 优。另外,介绍了 B*-tree 的表示方法以及它的几种操作步骤。还有对模拟退火 算法的思想、来源和步骤的详细介绍。阐述了自己对模拟退化算法的观点,和对 模拟退火算法的改进方案,使得得到最优解的可能性变大。
该论文有图19个,表6个,参考文献30篇。
毕业论文关键词:集成电路 模拟退火算法 B*树 布图规划
Floorplanning of Circuit Blocks Driven by Chip Area and Wirelength
Abstract Nowdays,intergrated circuit technology has made leaps and bounds because of the rapid development of information technology,The automatic floorplanning techniques of very large integration (VLSI) have been applied to various fields, such as computer,aerospace, civil and military electronics。 However,the world’s leading mamufacturers consider this kind of technology as the kernel secrets,and protect the technology。In our country, there are few companies that master the core technology of integrated circuits, so its market prospect is very broad。
This thesis describes the detailed steps of floorplanning in VLSI, as well as the representation methods of floorplanning。 Simulated annealing algorithm (SA) is used to solve the floorplanning of VLSI。 I explain the VLSI design process and one of the most critical physical design process。 The components of cost function are presented in order to optimize the chip area and wirelength。 In addition, the B*-tree representation is explicitly introduced, and its several operations are also given。 Furthermore, the idea, origin and a detailed description of the SA are elaborated。 There are several novel views on improved simulated annealing algorithm, which increases the chance of finding the optimal solutions。
Key words:Integrated circuit Simulated annealing algorithm B*- tree Floorplanning
目 录
摘 要 I
ABSTRACT II
目 录 III
图清单 IV
表清单 IV
1 绪论 1
1。1 课题研究背景及意义 1
1。3 本论文的主要工作 4
2 布图规划问题研究 5
2。1 VLSI设计流程 5
2。2 物理设计流程 6
2。3 布图规划中的成本函数的构成 9
3 布图规划常用算法及表示方法