摘要随着计算机技术的飞速发展，嵌入式系统受到了越来越多的关注。在高速图像采集 系统中，DDR 内存芯片是组成整个系统的关键部分，而 DDR 内存控制器在其中起着至 关重要的作用。FPGA 具有设计周期短且使用灵活的特点，同时 DDR3 SDRAM 是目前市 面上的主流内存芯片，其具有容量大、带宽高、实时性强的特点，因此两者已经广泛应 用于各个领域。

本文研究了基于 FPGA 平台的 DDR3 SDRAM 内存控制器的设计与实现，该设计不 仅为高速图像采集系统的存储方案提供了切实可行的方案，同时其具有可移植性强的特 点，可为其他嵌入式系统中的内存控制器提供解决方法。74308

本文在详细分析 DDR3 SDRAM 接口特性的基础上，针对其时序要求，研究其读写 指令的具体实现方法，设计了命令指令、读指令和写指令三类操作指令，同时比较当前 内存控制器的设计方案，实现了基于 FPGA 平台的 DDR 控制器整体方案；本设计的数据 来源是高速相机采集的图像信号通过 camera link 接口输入 FPGA 逻辑，将图像信号进行 解码后，经内存控制器写入至 DDR3 储存芯片中，在图像采集结束之后，再由内存控制 器将图像数据从芯片中读出，进行 UDP/IP 组包，经千兆以太网发送至 PC 机。本设计采 用自顶向下的设计思想，使用 VHDL 语言进行分模块设计，利用 Xilinx 公司内嵌在 ISE 软件内部的 IP 核 MIG tool，进行 DDR3 接口特性匹配设计，使得系统具备更高的可靠性， 针对设计过程中的关键部分，进行了详细的说明；利用 Spartan-6 系列芯片搭建 FPGA 平 台，将设计程序经综合、实现后，下载至 FPGA 平台进行读写验证。根据实验结果，内 存控制器能够正确地对 DDR3 芯片进行高速的读写操作，完全满足高速图像采集系统对 于高带宽和实时性的要求。

毕业论文关键词：FPGA DDR3 SDRAM 芯片 内存控制器 高速 VHDL

毕 业 设 计 说 明 书 外 文 摘 要

Title     Design of DDR Controller based on FPGA

Abstract With the rapid development of computer technology, the embedded system has arisen more and more attention。In a high-speed image acquisition system, the DDR memory chip is the key part of the whole system, and the DDR memory controller in which plays a important role。FPGA has the characteristics of short design cycle and flexible design, and DDR3 SDRAM is the market mainstream memory chip currently, which has the characteristics of large capacity, high bandwidth, strong real-time performance, both of them have been widely applied in various fields。

The paper have studied DDR3 SDRAM memory controller which based on the FPGA platform, the design and implementation of the design not only provides a feasible method for high-speed image acquisition system of storage solution , but also works as the memory controller in other embedded systems because of it’s portability。

The paper have based on the detailed analysis of DDR3 SDRAM interface features, focused on

its timing requirements, analyze its concrete realization method of the literacy instruction, design for three type of instruction,including command instruction 、 read instruction and write instruction, at the same time comparing the current memory controller design scheme,  designing

the DDR controller based on FPGA platform;This designer received data from a camera link interface of high speed camera image data, after decoding the image data , written to DDR3 chip by the memory controller, and at the end of the image acquisition, the memory controller will read out the image data from the chip in order to packaging as UDP/IP frame, finally through the gigabit Ethernet sent to computer。This subject used the top-down design method, used VHDL language for modular design, and used the Xilinx company embedded within the ISE software IP core MIG tool to matching the DDR3 interfaces feature,which can made the system has higher reliability。The paper has detailed description for the key part in the process of design;Made FPGA platform with Spartan-6 family chip, and take design  process  passed through synthesize, implementation, downloaded to the FPGA platform to verify the  operation of read and write。According to the experimental results, the memory controller can correctly to control DDR3 chip for high speed read and write operations, that can achieved the high-speed image acquisition system for high bandwidth and the requirement of real-time。