Abstract-This paper presents a fully synthesizable digital controller for high-frequency low-power DC-DC switching mode power supply (SMPS)。  Key module of the digital controller is a Hybrid digital pulse-width modulator (DPWM), which takes advantage of Digital Clock Manager (DCM) phase-shift characteristics available in FPGA resource and combines a counter-comparator with multi-bit Delta-Sigma (∆-Σ) Multi-stAge-noise-SHaping (MASH) modulator。  A digital controller which includes the proposed Hybrid ∆-Σ DPWM and a digital PID algorithm is experimentally verified using an FPGA on a high-frequency low-power discrete synchronous buck converter。  Experimental results with constant switching frequency up to 4MHz validate the functionality of the proposed digital controller。  In addition, the digital controller is implemented in a 0。35 μm standard CMOS。 84857

Keywords-Digital control, High-frequency low-power SMPS, 

Delta-Sigma DPWM, DCM phase-shift, FPGA implementation 

I。 INTRODUCTION 

Due to the numerous advantages including advanced control strategy, low sensitivity to variations, ability to use digital design tools and programmability to different implementation, digital controller has recently become an attractive candidate for high-frequency low-power switching mode power supply (SMPS) applications [1]-[10], where the high switching frequency is urgently required to reduce passive component size and to meet the system miniaturization demand。  A schematic diagram of a digital controller in SMPS application is shown in Fig。 1, where the digital controller consists of three blocks: Analog-to-Digital (A/D) Converter (ADC), Control Law and Digital Pulse-Width Modulator (DPWM)。 

In spite of so many apparent and potential benefits, some issues still require considering in practical digital control implementation, such as the sampling (ADC) delay, 

quantization error and the limited resolution of output voltage, which are focused by many power supply engineers。  The ADC resolution is becoming a less important issue thanks to window ADC techniques [5], [6]。  Thus the recent research on digital control has mainly been focused on two areas。  One is the methods to generate high-frequency high-resolution DPWM signals to meet the output voltage accuracy requirement and reduce the clock frequency requirement simultaneously。  The other is to develop high-performance control algorithm that can fully utilize the advantages of the digital control so as to improve the dynamic performance of the switching power converters。 

To increase the DPWM resolution in high-frequency operation while keeping the system clock frequency low, several alternative solutions have been proposed for high-resolution low-power DPWM, such as the hardware architectures: Counter-Comparator DPWM, counter-based Hybrid Delay-Line DPWM [4], [7], Segmented Delay-Line DPWM [3], [8], Ring-Oscillator DPWM [6], and the soft methods: Dither DPWM [9] and Delta-Sigma (∆-Σ) DPWM [10], [11]。  Each of the existing DPWM architectures has some advantages and disadvantages。  Counter-Comparator DPWM has the advantage of excellent linearity in the digital-to-time conversion, but it requires an ultra-high clock frequency。  Delay-Line, Segmented Delay-Line, Ring- Oscillator DPWM can be seen as similar type structures that use a series of tight logic cells to obtain the fine DPWM resolution while increase chip area。  Hybrid Delay-Line DPWM combines the counter- comparator with the delay-line as a trade-off between the high clock frequency and the chip area。  Soft methods Digital dither and ∆-Σ DPWM have been proven effective methods to design a high-resolution DPWM in software way without increasing chip area and power consumption。  Especially when DPWM comes to practical implementation in FPGA-based system, a very attractive digital technique, the Delay Locked Loop (DLL) [12], has recently been proposed to achieve DPWM。  It utilizes the available DLL phase-shift functional blocks in FPGA to reduce the required clock frequency。  In DLL DPWM, the most significant bits (MSBs) of PWM duty value are implemented by the counter-comparator and the least significant bits (LSBs) are implemented by the single/ or segmented DLL phase-shift block。