Based on the ∆-Σ noise-shaping technique and the DLL phase-shift function, this paper proposes a Hybrid DPWM, which takes advantage of Digital Clock Manager (DCM) phase-shift characteristics available in FPGA and combines a counter-comparator block with Multi-stAge-noise-SHaping (MASH) ∆-Σ modulator。  This Hybrid DPWM architecture can obtain a high-resolution DPWM while reducing clock frequency。  A digital controller including an 11-bit Hybrid ∆-Σ DPWM and classical PID control algorithm module is designed in detail and verified on a high-frequency low-power discrete buck converter by a Virtex-II FPGA。 

The paper is organized as follows: Section II describes the design of the 11-bit Hybrid ∆-Σ DPWM。  Section III shows simulation and experimental results of the proposed controller on a high-frequency low-power discrete synchronous buck converter。  Conclusions are given in section IV。 

II。 PROPOSED HYBRID ∆-Σ DPWM 

The proposed 11-bit Hybrid ∆-Σ DPWM includes three blocks: a 5-bit ∆-Σ modulator in soft method, a 4-bit segmented DCM phase-shift and a 2-bit counter-comparator in hardware architecture。  Fig。 2 shows the structure diagram of the proposed Hybrid ∆-Σ DPWM, and each block will be described in following sub-sections。 

A。 Multi-bit MASH ∆-Σ DPWM 

∆-Σ modulator has been widely used in A/D and D/A conversion。  It is based on the noise-shaping concept and can be implemented in low-cost CMOS technologies [13], [14]。  Fig。 3 shows the general structure of a single-stage ∆-Σ modulator for DPWM and its simplified schematic diagram。 

From the schematic diagram, the transfer function in linear model is given by 

V z( ) = Y z( )+ E z( ) ,              (1) 

where V(z) is the output duty value, E(z) is the truncation error。  Meanwhile, Y(z) can be expressed as: 

Y z( ) =U z( )− H z E ze( )⋅ ( ),           (2) 

where U(z) is the input duty value, He is generally a delay or integrator filter block。  Thus (1) can be rewritten as: 

V z( ) =U z( )+[1− H ze( )]⋅E z( ) ,         (3) 

Fig。 3。 Single-stage ∆-Σ modulator for DPWM with error feedback filter。 

which can be written in the general form: 

V z( ) = STF z U z( )⋅ ( )+ NTF z E z( )⋅ ( ) ,       (4) 

where STF(z) is the signal transfer function, and NTF(z) is the noise transfer function。  By setting the filter He as a delay (z–1), we can get STF(z)=1 and NTF(z)=(1–z–1) in (4)。  This equation shows how the noise transfer function NTF(z) influences the truncated signal。  In steady-state, the ∆-Σ loop has infinite gain at zero frequency (z ≈ 1)。  That is to say, it can significantly suppress the noise (||NTF(z)|| << 1) so that the input signal quantization error can be eliminated。 

⎨⎧⎪STF z( )≈1 ⇒V z( ) →U z( )          (5) 

⎪⎩NTF z( )1

From (5), it can be seen that the input PWM signal is almost unchanged as the quantization error is eliminated, and consequently, the output PWM duty value signal V(z) becomes approximately equal to the input PWM duty value signal U(z)。 

Based on the useful single-stage ∆-Σ modulator, a cascade modulator also called MASH ∆-Σ modulator [13] is adopted in this paper。  It has been proven that the MASH ∆-Σ modulator has the advantage to ease the stability problem evaluation in high-order ∆-Σ architecture [13], [14]。  The structure of a two-stage MASH ∆-Σ modulator is illustrated in Fig。 4。